View AM29LV640MU90RWHI_1101781.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

publication number 25301 revision c amendment 5 issue date february 1, 2007 this product has been retired and is not avai lable for designs. for new and current designs, s29gl064a supersedes am29lv640mu and is the fact ory-recommended migration path. please refer to the s29gl064a datasheet for specifications and ordering information. availability of this document is retained for reference an d historical purposes only. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansion product. any changes that have been made are the result of no rmal data sheet improvement and are noted in the document revision summary. for more information please contact your local sales office for additi onal information about spansion memory solutions. am29lv640mu data sheet retired product
this page left intentionally blank.
publication# 25301 rev: c amendment/ 5 issue date: february 1, 2007 data sheet am29lv640mu 64 megabit (4 m x 16-bit) mirrorbit ? 3.0 volt-only uniform sector fl ash memory with versatilei/o ? control distinctive characteristics architectural advantages ? single power supply operation ? 3 v for read, erase, and program operations ? versatilei/o ? control ? device generates data output voltages and tolerates data input voltages on the ce# and dq inputs/outputs as determined by the voltage on the v io pin; operates from 1.65 to 3.6 v ? manufactured on 0.23 m mirrorbit process technology ? secured silicon sector region ? 128-word sector for permane nt, secure identification through an 8-word random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? one hundred twenty-eight 32 kword sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection ? minimum 100,000 erase cycle guarantee per sector ? 20-year data retention at 125 c performance characteristics ? high performance ? 90 ns access time ? 25 ns page read times ? 0.5 s typical sector erase time ? 22 s typical effective write buffer word programming time: 16-word write buffer reduces overall programming time for multiple-word/byte updates ? 4-word page read buffer ? 16-word write buffer ? low power consumption (typical values at 3.0 v, 5 mhz) ? 30 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current ? package options ? 63-ball fine-pitch bga ? 64-ball fortified bga software & hardware features ? software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word programming time ? cfi (common flash interface) compliant: allows host system to identify and ac commodate multiple flash devices ? hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level method of changing code in locked sectors ? acc (high voltage) input accelerates programming time for higher throughput during system production ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) indicates program or erase cycle completion this product has been retired and is not available for designs. for new and current designs, s29gl064a supersedes am29lv640m u and is the factory-recommended migration path. please refer to the s29gl064a datasheet for specifications and orderi ng information. availability of this document is retained for reference and historical purposes only.
2 am29lv640mu 25301c5 february 1, 2007 data sheet general description the am29lv640mu is a 64 mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words. the device has a 16-bit only data bus, and can be programmed either in the host system or in stan- dard eprom programmers. an access time of 90, 100, 110, or 120 ns is available. note that each access time has a specific operating voltage range (v cc ) and an i/o voltage range (v io ), as specified in the product selector guide and the order- ing information sections. the device is offered in a 63-ball fine-pitch bga or 64-ball fortified bga pack- age. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program (acc) input provides shorter programming times through increased current. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase oper- ation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to deter- mine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. the versatilei/o? (v io ) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the ce# control input and dq i/os to the same voltage level that is asserted on the v io pin. refer to the ordering information section for valid v io options. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program sus- pend/program resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secured silicon sector provides a 128-word area for code or data that can be permanently pro- tected. once this sector is protected, no further changes within the sector can occur. amd mirrorbit flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
february 1, 2007 25301c5 am29lv640mu 3 data sheet mirrorbit 64 mbit device family related documents to download related documents, click on the following links or go to www.amd.com flash memory prod- uct information mirrorbit flash information te c h - nical documentation. mirrorbit? flash memory write buffer programming and page buffer read implementing a common layout for amd mirrorbit and intel strataflash memory devices amd mirrorbit? white paper migrating from single-byte to three-byte device ids migration from am29lv640du to mirrorbit am29lv640mu device bus sector architecture packages v io ry/by# wp#, acc wp# protection lv065mu x8 uniform (64 kbyte) 48-pin tsop (std. & rev. pinout), 63-ball fbga yes yes acc only no wp# lv640mt/b x8/x16 boot (8 x 8 kbyte at top & bottom) 48-pin tsop, 63-ball fine-pitch bga, 64-ball fortified bga no yes wp#/acc pin 2 x 8 kbyte top or bottom lv640mh/l x8/x16 uniform (64 kbyte) 56-pin tsop (std. & rev. pinout), 64 fortified bga yes yes wp#/acc pin 1 x 64 kbyte high or low lv641mh/l x16 uniform (32 kword) 48-pin tsop (std. & rev. pinout) yes no separate wp# and acc pins 1 x 32 kword top or bottom lv640mu x16 uniform (32 kword) 63-ball fine-pitch bga, 64-ball fortified bga yes yes acc only no wp#
4 am29lv640mu 25301c5 february 1, 2007 data sheet table of contents mirrorbit 64 mbit device family . . . . . . . . . . . . . . 3 product selector guide . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 6 special package handling instructions .................................... 7 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . 9 device bus operations . . . . . . . . . . . . . . . . . . . . 10 table 1. device bus operations .....................................................10 versatileio ? (v io ) control ..................................................... 10 requirements for reading array data ................................... 10 page mode read .................................................................... 11 writing commands/command sequences ............................ 11 write buffer ............................................................................. 11 accelerated program operation ............................................. 11 autoselect functions .............................................................. 11 standby mode ........................................................................ 11 automatic sleep mode ........................................................... 11 reset#: hardware reset pin ............................................... 12 output disable mode .............................................................. 12 table 2. sector address table ........................................................13 autoselect mode..................................................................... 15 table 3. autoselect codes, (high voltage method) .......................15 sector group protection and unprotection ............................. 16 table 4. sector group protection/unprotection address table .....16 temporary sector group unprotect ....................................... 17 figure 1. temporary sector group unprotect operation................ 17 figure 2. in-system sector group protect/unprotect algorithms ... 18 secured silicon sector flash memory region ....................... 19 table 5. secured silicon sector contents ......................................19 figure 3. secured silicon sector protect verify .............................. 20 hardware data protection ...................................................... 20 low vcc write inhibit ............................................................ 20 write pulse ?glitch? protection ............................................... 20 logical inhibit .......................................................................... 20 power-up write inhibit ............................................................ 20 common flash memory interface (cfi) . . . . . . . 21 table 6. cfi query identification string .............................. 21 table 7. system interface string......................................................21 table 8. device geometry definition................................... 22 table 9. primary vendor-specific extended query............. 23 command definitions . . . . . . . . . . . . . . . . . . . . . 24 reading array data ................................................................ 24 reset command ..................................................................... 24 autoselect command sequence ............................................ 24 enter secured silicon sector/exit secured silicon sector command sequence .............................................................. 25 word program command sequence ..................................... 25 unlock bypass command sequence ..................................... 25 write buffer programming ...................................................... 25 accelerated program .............................................................. 26 figure 4. write buffer programming operation............................... 27 figure 5. program operation .......................................................... 28 program suspend/program resume command sequence ... 28 figure 6. program suspend/program resume............................... 29 chip erase command sequence ........................................... 29 sector erase command sequence ........................................ 29 erase suspend/erase resume commands ........................... 30 figure 7. erase operation.............................................................. 30 command definitions ............................................................. 31 table 10. command definitions...................................................... 31 write operation status . . . . . . . . . . . . . . . . . . . . . 32 dq7: data# polling ................................................................. 32 figure 8. data# polling algorithm .................................................. 32 ry/by#: ready/busy#............................................................ 33 dq6: toggle bit i .................................................................... 33 figure 9. toggle bit algorithm........................................................ 34 dq2: toggle bit ii ................................................................... 34 reading toggle bits dq6/dq2 ............................................... 34 dq5: exceeded timing limits ................................................ 35 dq3: sector erase timer ....................................................... 35 dq1: write-to-buffer abort ..................................................... 35 table 11. write operation status ................................................... 35 absolute maximum ratings. . . . . . . . . . . . . . . . . 36 figure 10. maximum negative overshoot waveform ................... 36 figure 11. maximum positive overshoot waveform..................... 36 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 36 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 12. test setup.................................................................... 38 table 12. test specifications ......................................................... 38 key to switching waveforms. . . . . . . . . . . . . . . . 38 figure 13. input waveforms and measurement levels...................................................................... 38 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39 read-only operations ........................................................... 39 figure 14. read operation timings ............................................... 39 figure 15. page read timings ...................................................... 40 hardware reset (reset#) .................................................... 41 figure 16. reset timings ............................................................... 41 erase and program operations .............................................. 42 figure 17. program operation timings.......................................... 43 figure 18. accelerated program timing diagram.......................... 43 figure 19. chip/sector erase operation timings .......................... 44 figure 20. data# polling timings (during embedded algorithms)...................................................... 45 figure 21. toggle bit timings (during embedded algorithms)...................................................... 46 figure 22. dq2 vs. dq6................................................................. 46 temporary sector unprotect .................................................. 47 figure 23. temporary sector group unprotect timing diagram ... 47 figure 24. sector group protect and unprotect timing diagram .. 48 alternate ce# controlled erase and program operations ..... 49 figure 25. alternate ce# controlled write (erase/program) operation timings.......................................................................... 50 erase and programming performance. . . . . . . . 51 latchup characteristics . . . . . . . . . . . . . . . . . . . . 51 tsop pin and fine-pitch bga package capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 53 laa064?64-ball fortified ball grid array ( f bga) 13 x 11 mm package .............................................................. 53 fbe063?63-ball fine-pitch ball grid array (fbga) 12 x 11 mm package .............................................................. 54 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 55
february 1, 2007 25301c5 am29lv640mu 5 data sheet product selector guide notes: 1. see ?ac characteristics? for full specifications. 2. for the am29lv640mu device, the last numeric digit in the speed option (e.g. 101 , 112 , 120 ) is used for internal purposes only. please use opns as listed when placing orders. block diagram part number am29lv640mu speed option v cc = 3.0?3.6 v 90r (v io = 3.0?3.6 v) 101r (v io = 2.7?3.6 v) 112r (v io = 1.65?3.6 v) 120r (v io = 1.65?3.6 v) v cc = 2.7?3.6 v 101 (v io = 2.7?3.6 v) 112 (v io = 1.65?3.6 v) 120 (v io = 1.65?3.6 v) max. access time (ns) 90 100 110 120 max. ce# access time (ns) 90 100 110 120 max. page access time (t pac c )25 30 30 40 30 40 max. oe# access time (ns) 25 30 30 40 30 40 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# acc ce# oe# stb stb dq0 ? dq15 sector switches ry/by# reset# data latch y-gating cell matrix address latch a21?a0
6 am29lv640mu 25301c5 february 1, 2007 data sheet connection diagrams b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b8 c8 d8 e8 f8 g8 h8 nc nc nc v ss v io nc nc v ss dq15/a-1 nc a16 a15 a14 a12 dq6 dq13 dq14 dq7 a11 a10 a8 dq4 v cc dq12 dq5 a19 a21 reset# dq3 dq11 dq10 dq2 a20 a18 acc dq1 dq9 dq8 dq0 a5 a6 a17 a3 a4 a5 a6 a7 a8 nc a13 a9 we# ry/by# a7 b2 c2 d2 e2 f2 g2 h2 v ss oe# ce# a0 a1 a2 a4 a2 a3 b1 c1 d1 e1 f1 g1 h1 nc nc v io nc nc nc nc a1 nc 64-ball fortified bga top view, balls facing down
february 1, 2007 25301c5 am29lv640mu 7 data sheet connection diagrams special package ha ndling instructions special handling is required for flash memory products in molded packages (tsop, bga, ssop, pdip, plcc). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. c2 d2 e2 f2 g2 h2 j2 k2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 c5 d5 e5 f5 g5 h5 j5 k5 c6 d6 e6 f6 g6 h6 j6 k6 c7 d7 a7 b7 a8 b8 a1 b1 a2 e7 f7 g7 h7 j7 k7 l7 l8 m7 m8 l1 l2 m1 m2 nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc nc nc nc dq15 v ss v io a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 * balls are shorted together via the substrate but not connected to the die. 63-ball fine-pitch bga top view, balls facing down
8 am29lv640mu 25301c5 february 1, 2007 data sheet pin description a21?a0 = 22 address inputs dq15?dq0 = 15 data inputs/outputs ce# = chip enable input oe# = output enable input we# = write enable input acc = programming acceleration input reset# = hardware reset pin input ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss = device ground nc = pin not connected internally logic symbol 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# ry/by# acc v io
february 1, 2007 25301c5 am29lv640mu 9 data sheet ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: note: for the am29lv640mu device, the last numeric digit in the speed option (e.g. 101 , 112 , 120 ) is used for internal purposes only. use opns as listed when placing orders. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of spe- cific valid combinations and to check on newly released combinations. am29lv640m u 120r pc i temperature range i = industrial (?40 c to +85 c) package type pc = 64-ball fortified ball grid array, 1.0 mm pitch, 13 x 11 mm package (laa064) wh = 63-ball fine pitch ball grid array, 0.80 mm pitch, 12 x 11 mm package (fbe063) speed option see product selector guide and valid combinations sector architecture u = uniform sector device device number/description am29lv640mu 64 megabit (4 m x 16-bit) mirrorbit ? uniform sector flash memory with versatileio ? control, 3.0 volt-only read, program, and erase valid combinations for fortified or fine-pitch bga package speed (ns) v io range v cc range order number package marking am29lv640mu90r whi l640mu90r i90 3.0? 3.6 v 3.0? 3.6 v pci l640mu90n am29lv640mu101 whi l640mu01v i 100 2.7? 3.6 v 2.7? 3.6 v pci l640mu01p am29lv640mu112 whi l640mu11v i 110 1.65? 3.6 v pci l640mu11p am29lv640mu120 whi, l640mu12v i 120 1.65? 3.6 v pci l640mu12p am29lv640mu101r whi, l640mu01r i 100 2.7? 3.6 v 3.0? 3.6 v pci l640mu01n am29lv640mu112r whi, l640mu11r i 110 1.65? 3.6 v pci l640mu11n am29lv640mu120r whi, l640mu12r i 120 1.65? 3.6 v pci l640mu12n
10 am29lv640mu 25301c5 february 1, 2007 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta bl e 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a21:a0. sector addresses are a21:a15. 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 3. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). versatileio ? (v io ) control the versatileio? (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on ce# and dq i/os to the same voltage level that is asserted on v io . see ?ordering informa- tion? on page 9 for v io options on this device. for example, a v i/o of 1.65?3.6 volts allows for i/o at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 v devices on the same data bus. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only operations table for timing speci- fications and to figure 13 for the timing diagram. refer operation ce# oe# we# reset# acc addresses (note 2) dq0? dq15 read l l h h x a in d out write (program/erase) l h l h x a in (note 3) accelerated program l h l h v hh a in (note 3) standby v cc 0.3 v xx v cc 0.3 v h xhigh-z output disable l h h h x xhigh-z reset x x x l x xhigh-z sector group protect (note 2) l h l v id x sa, a6=l, a3=l, a2=l, a1=h, a0=l (note 3) sector group unprotect (note 2) lhl v id x sa, a6=h, a3=l, a2=l, a1=h, a0=l (note 3) temporary sector group unprotect xxx v id x a in (note 3)
february 1, 2007 25301c5 am29lv640mu 11 data sheet to the dc characteristics table for the active current specification for reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words. the appropriate page is se- lected by the higher address bits a(max)?a2. address bits a1?a0 determine the specific word within a page. this is an asynchronous operation; the microproces- sor supplies the specif ic word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pac c . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode ac- cesses are obtained by keeping the ?read-page ad- dresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word, instead of four. the word program command sequence section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. ta b l e 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac char- acteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system to write a maximum of 16 words in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the acc pin returns the device to normal op- eration. note that the acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autose lect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. standby mode when the system is not read ing or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. refer to the dc characteristics table for the standby current spec ification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and alwa ys available to the system. refer to the dc characteristics table for the automatic sleep mode current specification.
12 am29lv640mu 25301c5 february 1, 2007 data sheet reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for th e duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current. if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase op- eration, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the sys- tem can thus monitor ry/by# to determine whether the reset operation is comp lete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the re- set# pin returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 15 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
february 1, 2007 25301c5 am29lv640mu 13 data sheet table 2. sector address table sector a21?a15 16-bit address range (in hexadecimal) sector a21?a15 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 0 000000?007fff sa32 0 1 0 0 0 0 0 100000?107fff sa1 0 0 0 0 0 0 1 008000?00ffff sa33 0 1 0 0 0 0 1 108000?10ffff sa2 0 0 0 0 0 1 0 010000?017fff sa34 0 1 0 0 0 1 0 110000?117fff sa3 0 0 0 0 0 1 1 018000?01ffff sa35 0 1 0 0 0 1 1 118000?11ffff sa4 0 0 0 0 1 0 0 020000?027fff sa36 0 1 0 0 1 0 0 120000?127fff sa5 0 0 0 0 1 0 1 028000?02ffff sa37 0 1 0 0 1 0 1 128000?12ffff sa6 0 0 0 0 1 1 0 030000?037fff sa38 0 1 0 0 1 1 0 130000?137fff sa7 0 0 0 0 1 1 1 038000?03ffff sa39 0 1 0 0 1 1 1 138000?13ffff sa8 0 0 0 1 0 0 0 040000?047fff sa40 0 1 0 1 0 0 0 140000?147fff sa9 0 0 0 1 0 0 1 048000?04ffff sa41 0 1 0 1 0 0 1 148000?14ffff sa10 0 0 0 1 0 1 0 050000?057fff sa42 0 1 0 1 0 1 0 150000?157fff sa11 0 0 0 1 0 1 1 058000?05ffff sa43 0 1 0 1 0 1 1 158000?15ffff sa12 0 0 0 1 1 0 0 060000?067fff sa44 0 1 0 1 1 0 0 160000?167fff sa13 0 0 0 1 1 0 1 068000?06ffff sa45 0 1 0 1 1 0 1 168000?16ffff sa14 0 0 0 1 1 1 0 070000?077fff sa46 0 1 0 1 1 1 0 170000?177fff sa15 0 0 0 1 1 1 1 078000?07ffff sa47 0 1 0 1 1 1 1 178000?17ffff sa16 0 0 1 0 0 0 0 080000?087fff sa48 0 1 1 0 0 0 0 180000?187fff sa17 0 0 1 0 0 0 1 088000?08ffff sa49 0 1 1 0 0 0 1 188000?18ffff sa18 0 0 1 0 0 1 0 090000?097fff sa50 0 1 1 0 0 1 0 190000?197fff sa19 0 0 1 0 0 1 1 098000?09ffff sa51 0 1 1 0 0 1 1 198000?19ffff sa20 0 0 1 0 1 0 0 0a0000?0a7fff sa52 0 1 1 0 1 0 0 1a0000?1a7fff sa21 0 0 1 0 1 0 1 0a8000?0affff sa53 0 1 1 0 1 0 1 1a8000?1affff sa22 0 0 1 0 1 1 0 0b0000?0b7fff sa54 0 1 1 0 1 1 0 1b0000?1b7fff sa23 0 0 1 0 1 1 1 0b8000?0bffff sa55 0 1 1 0 1 1 1 1b8000?1bffff sa24 0 0 1 1 0 0 0 0c0000?0c7fff sa56 0 1 1 1 0 0 0 1c0000?1c7fff sa25 0 0 1 1 0 0 1 0c8000?0cffff sa57 0 1 1 1 0 0 1 1c8000?1cffff sa26 0 0 1 1 0 1 0 0d0000?0d7fff sa58 0 1 1 1 0 1 0 1d0000?1d7fff sa27 0 0 1 1 0 1 1 0d8000?0dffff sa59 0 1 1 1 0 1 1 1d8000?1dffff sa28 0 0 1 1 1 0 0 0e0000?0e7fff sa60 0 1 1 1 1 0 0 1e0000?1e7fff sa29 0 0 1 1 1 0 1 0e8000?0effff sa61 0 1 1 1 1 0 1 1e8000?1effff sa30 0 0 1 1 1 1 0 0f0000?0f7fff sa62 0 1 1 1 1 1 0 1f0000?1f7fff sa31 0 0 1 1 1 1 1 0f8000?0fffff sa63 0 1 1 1 1 1 1 1f8000?1fffff sa64 1 0 0 0 0 0 0 200000?207fff sa96 1 1 0 0 0 0 0 300000?307fff sa65 1 0 0 0 0 0 1 208000?20ffff sa97 1 1 0 0 0 0 1 308000?30ffff sa66 1 0 0 0 0 1 0 210000?217fff sa98 1 1 0 0 0 1 0 310000?317fff sa67 1 0 0 0 0 1 1 218000?21ffff sa99 1 1 0 0 0 1 1 318000?31ffff sa68 1 0 0 0 1 0 0 220000?227fff sa100 1 1 0 0 1 0 0 320000?327fff sa69 1 0 0 0 1 0 1 228000?22ffff sa101 1 1 0 0 1 0 1 328000?32ffff sa70 1 0 0 0 1 1 0 230000?237fff sa102 1 1 0 0 1 1 0 330000?337fff sa71 1 0 0 0 1 1 1 238000?23ffff sa103 1 1 0 0 1 1 1 338000?33ffff sa72 1 0 0 1 0 0 0 240000?247fff sa104 1 1 0 1 0 0 0 340000?347fff sa73 1 0 0 1 0 0 1 248000?24ffff sa105 1 1 0 1 0 0 1 348000?34ffff sa74 1 0 0 1 0 1 0 250000?257fff sa106 1 1 0 1 0 1 0 350000?357fff sa75 1 0 0 1 0 1 1 258000?25ffff sa107 1 1 0 1 0 1 1 358000?35ffff
14 am29lv640mu 25301c5 february 1, 2007 data sheet note: all sectors are 32 kwords in size. sa76 1 0 0 1 1 0 0 260000?267fff sa108 1 1 0 1 1 0 0 360000?367fff sa77 1 0 0 1 1 0 1 268000?26ffff sa109 1 1 0 1 1 0 1 368000?36ffff sa78 1 0 0 1 1 1 0 270000?277fff sa110 1 1 0 1 1 1 0 370000?377fff sa79 1 0 0 1 1 1 1 278000?27ffff sa111 1 1 0 1 1 1 1 378000?37ffff sa80 1 0 1 0 0 0 0 280000?287fff sa112 1 1 1 0 0 0 0 380000?387fff sa81 1 0 1 0 0 0 1 288000?28ffff sa113 1 1 1 0 0 0 1 388000?38ffff sa82 1 0 1 0 0 1 0 290000?297fff sa114 1 1 1 0 0 1 0 390000?397fff sa83 1 0 1 0 0 1 1 298000?29ffff sa115 1 1 1 0 0 1 1 398000?39ffff sa84 1 0 1 0 1 0 0 2a0000?2a7fff sa116 1 1 1 0 1 0 0 3a0000?3a7fff sa85 1 0 1 0 1 0 1 2a8000?2affff sa117 1 1 1 0 1 0 1 3a8000?3affff sa86 1 0 1 0 1 1 0 2b0000?2b7fff sa118 1 1 1 0 1 1 0 3b0000?3b7fff sa87 1 0 1 0 1 1 1 2b8000?2bffff sa119 1 1 1 0 1 1 1 3b8000?3bffff sa88 1 0 1 1 0 0 0 2c0000?2c7fff sa120 1 1 1 1 0 0 0 3c0000?3c7fff sa89 1 0 1 1 0 0 1 2c8000?2cffff sa121 1 1 1 1 0 0 1 3c8000?3cffff sa90 1 0 1 1 0 1 0 2d0000?2d7fff sa122 1 1 1 1 0 1 0 3d0000?3d7fff sa91 1 0 1 1 0 1 1 2d8000?2dffff sa123 1 1 1 1 0 1 1 3d8000?3dffff sa92 1 0 1 1 1 0 0 2e0000?2e7fff sa124 1 1 1 1 1 0 0 3e0000?3e7fff sa93 1 0 1 1 1 0 1 2e8000?2effff sa125 1 1 1 1 1 0 1 3e8000?3effff sa94 1 0 1 1 1 1 0 2f0000?2f7fff sa126 1 1 1 1 1 1 0 3f0000?3f7fff sa95 1 0 1 1 1 1 1 2f8000?2fffff sa127 1 1 1 1 1 1 1 3f8000?3fffff table 2. sector address table (continued) sector a21?a15 16-bit address range (in hexadecimal) sector a21?a15 16-bit address range (in hexadecimal)
february 1, 2007 25301c5 am29lv640mu 15 data sheet autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-syste m through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in ta bl e 3 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 2 ). ta b l e 3 shows the remain- ing address bits that are don?t care. when all neces- sary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in ta b l e 1 0 . this method does not require v id . refer to the autoselect com- mand sequence section for more information. table 3. autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. description ce# oe# we# a21 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq15 to dq0 manufacturer id : amd l l h x x v id x l x l l l 0001h device id cycle 1 ll h x x v id xlx llh 227eh cycle 2 h h l 2213h cycle 3 h h h 2201h sector protection ver ification ll hsax v id xlxlhl xx01h (protected), xx00h (unprotected) secured silicon sector indicator bit (dq7) ll h x x v id xlxlhh xx98h (factory locked), xx18h (not factory locked)
16 am29lv640mu 25301c5 february 1, 2007 data sheet sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see ta b l e 4 ). the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/unprotection can be implemented via two methods. sector protection/unprotection requires v id on the re- set# pin only, and can be implemented either in-sys- tem or via programming equipment. figure 2 shows the algorithms and figure 23 shows the timing dia- gram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unpro- tected sector groups must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and pro- tecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. con- tact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. table 4. sector group protection/unprotection address table note: all sector groups are 128 kwords in size. sector group a21?a17 sa0?sa3 00000 sa4?sa7 00001 sa8?sa11 00010 sa12?sa15 00011 sa16?sa19 00100 sa20?sa23 00101 sa24?sa27 00110 sa28?sa31 00111 sa32?sa35 01000 sa36?sa39 01001 sa40?sa43 01010 sa44?sa47 01011 sa48?sa51 01100 sa52?sa55 01101 sa56?sa59 01110 sa60?sa63 01111 sa64?sa67 10000 sa68?sa71 10001 sa72?sa75 10010 sa76?sa79 10011 sa80?sa83 10100 sa84?sa87 10101 sa88?sa91 10110 sa92?sa95 10111 sa96?sa99 11000 sa100?sa103 11001 sa104?sa107 11010 sa108?sa111 11011 sa112?sa115 11100 sa116?sa119 11101 sa120?sa123 11110 sa124?sa127 11111
february 1, 2007 25301c5 am29lv640mu 17 data sheet temporary sector group unprotect ( note: in this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see ta b l e 4 ). this feature allows temporary unprotection of previ- ously protected sector group s to change data in-sys- tem. the sector group unprotect mode is activated by setting the reset# pin to vid . during this mode, for- merly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previously protected sector groups are protected again. figure 1 shows the algorithm, and figure 22 shows the timing diagrams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected. 2. all previously protected sector groups are protected once again.
18 am29lv640mu 25301c5 february 1, 2007 data sheet figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6?a0 = 0xx0010 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6?a0 = 0xx0010 read from sector group address with a6?a0 = 0xx0010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6?a0 = 1xx0010 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6?a0 = 1xx0010 read from sector group address with a6?a0 = 1xx0010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
february 1, 2007 25301c5 am29lv640mu 19 data sheet secured silicon sector flash memory region the secured silicon sector feature provides a flash memory region that enables permanent part identifica- tion through an electronic serial number (esn). the secured silicon sector is 128 words in length, and uses a secured silicon sector indicator bit (dq7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is per- manently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. amd offers the device with the secured silicon sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secured silicon sector unprotected, allowing cust omers to pro- gram the sector after receiving the device. the cus- tomer-lockable version also has the secured silicon sector indicator bit permanently set to a ?0.? thus, the secured silicon sector indicator bit prevents cus- tomer-lockable devices from being used to replace de- vices that are factory locked. the secured silicon sector address space in this de- vice is allocated as follows: the system accesses the secured silicon sector through a command sequence (see ?enter secured silicon sector/exit secured silicon sector command sequence?). after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secured si licon sector command se- quence, or until power is removed from the device. on power-up, or following a hardware reset, the device re- verts to sending comma nds to sector sa0. factory locked: secured silicon sector programmed and protected at the factory in devices with an esn, the secured silicon sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. see ta b l e 5 for secured silicon sector address- ing. customers may opt to have their code programmed by amd through the amd expre ssflash service. the de- vices are then shipped from amd?s factory with the secured silicon sector permanently locked. contact an amd representative for details on using amd?s ex- pressflash service. customer lockable: secured silicon sector not programmed or protected at the factory as an alternative to the factory-locked version, the de- vice may be ordered such that the customer may pro- gram and protect the 128-word secured silicon sector. the system may program the secured silicon sector using the write-buffer, accelerated and/or unlock by- pass methods, in addition to the standard program- ming command sequence. see command definitions . programming and protecting the secured silicon sec- tor must be used with caution since, once protected, there is no procedure available for unprotecting the secured silicon sect or area and none of the bits in the secured silicon sector memory space can be modi- fied in any way. the secured silicon sector area can be protected using one of the following procedures: write the three-cycle enter secured silicon sector region command sequence, and then follow the in-system sector protect algorithm as shown in fig- ure 2, except that reset# may be at either v ih or v id . this allows in-system protection of the secured silicon sector without raising any device pin to a high voltage. note that this method is only applica- ble to the secured silicon sector. to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure 3 . once the secured silicon sector is programmed, locked and verified, the system must write the exit se- cured silicon sector re gion command sequence to return to reading and writing within the remainder of the array. table 5. secured silicon sector contents secured silicon sector address range standard factory locked expressflash factory locked customer lockable 000000h?000007h esn esn or determined by customer determined by customer 000008h?00007fh unavailable determined by customer
20 am29lv640mu 25301c5 february 1, 2007 data sheet figure 3. secured silicon sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 ms read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
february 1, 2007 25301c5 am29lv640mu 21 data sheet common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cf i query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6?9. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6?9. the system must write the reset command to return the device to reading array data. for further information, plea se refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alterna- tively, contact an amd representative for copies of these documents. table 6. cfi query identification string table 7. system interface string addresses (x16) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0007h typical timeout per single word write 2 n s 20h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0001h max. timeout for word write 2 n times typical 24h 0005h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
22 am29lv640mu 25301c5 february 1, 2007 data sheet table 8. device geometry definition addresses (x16) data description 27h 0017h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) (00h not supported) 2ah 2bh 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 007fh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
february 1, 2007 25301c5 am29lv640mu 23 data sheet table 9. primary vendor-specific extended query addresses (x16) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0008h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0004h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0004h sector protect/ unprotect scheme 04 = 29lv800 mode 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0001h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0000h top/bottom boot sector flag 00h = uniform device without wp# protec t, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h 0001h program suspend 00h = not supported, 01h = supported
24 am29lv640mu 25301c5 february 1, 2007 data sheet command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 10 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens la ter. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. see the next section, reset command , for more informa- tion. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 13 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an aut oselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer pro- gramming operation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: note: the device id is read over thr ee cycles. sa = sector address table 10 shows the address and data requirements. this method is an alternative to that shown in ta bl e 3 , which is intended for prom programmers and re- quires v id on address pin a9. the autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the de- vice is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). identifier code a7:a0 manufacturer id 00h device id, cycle 1 01h device id, cycle 2 0eh device id, cycle 3 0fh secured silicon sector factory protect 03h sector protect verify (sa)02h
february 1, 2007 25301c5 am29lv640mu 25 data sheet enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing an 8-word random electronic se- rial number (esn). the system can access the se- cured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four-cycle exit secured silicon sector command sequence. the exit secured silicon sector command sequence re- turns the device to normal operation. ta b l e 1 0 shows the address and data requirements for both command sequences. see also secured silicon sector flash memory region for further information. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 10 shows the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write operation status section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeedin g read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two un- lock cycles. this is followed by a third write cycle con- taining the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle un- lock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program com- mand, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. ta bl e 1 0 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to the read mode. write buffer programming write buffer programming allows the system write to a maximum of 16 words in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load com- mand written at the sector address in which program- ming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for exam ple, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the writ e buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. a write-buffer-page is se- lected by address bits a max ?a 4 . all subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer locations may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be per- formed across multiple write-buffer pages. this also means that write buffer programming cannot be per- formed across multiple sector s. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the address/data pair counter will be
26 am29lv640mu 25301c5 february 1, 2007 data sheet decremented for every data load operation. the host system must therefore account for loading a write-buffer location more than once. the counter dec- rements for each data load operation, not for each unique write-buffer-address location. additionally, the last data loaded prior to the program buffer to flash command will be programmed into the device. note also that if an address location is loaded more than once into the buffer, the final data loaded for that ad- dress will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the pro- gram buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitoring the last add ress location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: load a value that is greater than the page buffer size during the number of locations to program step. write to an address in a sector different than the one specified during the write-buffer-load com- mand. write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data load- ing stage of the operation. write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset command sequence must be written to reset the de- vice for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is re- quired when using write-buffer-programming features in unlock bypass mode. accelerated program the device offers accelerated program operations through the acc pin. when the system asserts v hh on the acc pin, the device automatically enters the un- lock bypass mode. the system may then write the two-cycle unlock bypass program command se- quence. the device uses the higher voltage on the acc pin to accelerate the operation. note that the acc pin must not be at v hh for operations other than accelerated programming, or device damage may re- sult. figure 4 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 16 for timing diagrams.
february 1, 2007 25301c5 am29lv640mu 27 data sheet figure 4. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write-buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see ta b l e 1 0 for command sequences required for write buffer programming. (note 3) (note 1) (note 2)
28 am29lv640mu 25301c5 february 1, 2007 data sheet figure 5. program operation program suspend/pr ogram resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program sus- pend command is written during a programming pro- cess, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not required when writing the program suspend command. after the programming operation has been sus- pended, the system can read array data from any non-suspended sector. the program suspend com- mand may also be issued during a programming oper- ation while an erase is suspended. in this case, data may be read from any addresses not in erase sus- pend or program suspend. if a read is needed from the secured silicon sector area (one-time program area), then user must use the proper command se- quences to enter and exit this region. the system may also writ e the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to programming. the system can deter- mine the status of the program operation using the dq7 or dq6 status bits, just as in the standard pro- gram operation. see write operation status for more information. the system must write th e program resume com- mand (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ig- nored. another program suspend command can be written after the device has resume programming. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 10 for program command sequence.
february 1, 2007 25301c5 am29lv640mu 29 data sheet figure 6. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initia ted by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 10 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 18 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 10 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must re- write the command sequence and any additional ad- dresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
30 am29lv640mu 25301c5 february 1, 2007 data sheet when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characterist ics section for parameters, and figure 18 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sec- tor erase operation, including the 50 s time-out pe- riod during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typi- cal of 5 s (maximum 20 s) to suspend the erase op- eration. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. after the erase operation has been suspended, the device enters the erase-su spend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. note: during an erase operation, this flash device per- forms multiple internal operations which are invisible to the system. when an erase operation is suspended, any of the internal operations that were not fully com- pleted must be restarted. as such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the number of suspends. the result will be a longer cumulative erase time than without suspends. note that the additional suspends do not affect device reliability or future performa nce. in most systems rapid erase/suspend activity occurs only briefly. in such cases, erase performance will not be significantly im- pacted. figure 7. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 10 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
february 1, 2007 25301c5 am29lv640mu 31 data sheet command definitions table 10. command definitions legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes: 1. see ta b l e 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or 2aa as shown in table, address bits higher than a11 and data bits higher than dq7 are don?t care. 5. unless otherwise noted, address bits a21?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high (while the device is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care, except for rd, pd and wc. see the autoselect command sequence section for more information. 9. the device id must be read in three cycles. 10. the data is 98h for factory locked and 18h for not factory locked. 11. the data is 00h for an unprotected sector group and 01h for a protected sector group. 12. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 21, including "program buffer to flash" command. 13. command sequence resets device for next command after aborted write-to-buffer operation. 14. the unlock bypass command is required prior to the unlock bypass program command. 15. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 17. the erase resume command is valid only during the erase suspend mode. 18. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (notes) cycles bus cycles (notes 1?4) addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 9) 6 555 aa 2aa 55 555 90 x01 227e x0e 2213 x0f 2201 secured silicon sector factory protect (note 10) 4 555 aa 2aa 55 555 90 x03 (note 10) sector group protect verify (note 11) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secured silicon sector region 3 555 aa 2aa 55 555 88 exit secured silicon sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 12) 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 13) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 14) 2 xxx a0 pa pd unlock bypass reset (note 15) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 16) 1 xxx b0 program/erase resume (note 17) 1 xxx 30 cfi query (note 18) 1 55 98
32 am29lv640mu 25301c5 february 1, 2007 data sheet write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 11 and the following subs ections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is com- plete or in progress. the device also provides a hard- ware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on suc- cessive read cycles. table 11 shows the outputs for data# polling on dq7. figure 7 shows the data# po lling algorithm. figure 19 in the ac characteristics section shows the data# polling timing diagram. figure 8. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being eras ed. during chip erase, a valid address is any non- protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
february 1, 2007 25301c5 am29lv640mu 33 data sheet ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or the device is in the erase-suspend-read mode. table 11 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read c ycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 11 shows the outputs for toggle bit i on dq6. figure 8 shows the toggle bit algorithm. figure 20 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 21 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii .
34 am29lv640mu 25301c5 february 1, 2007 data sheet figure 9. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 11 to compare out- puts for dq2 and dq6. figure 8 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. figure 20 shows the toggle bit timing diagram. figure 21 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 8 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
february 1, 2007 25301c5 am29lv640mu 35 data sheet other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 8). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not suc- cessfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de termine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 1 1 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort-reset command sequence to re- turn the device to reading array data. see write buffer table 11. write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedde d erase, or write-to-buffer operation has exceeded the maximum timing limits. re fer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
36 am29lv640mu 25301c5 february 1, 2007 data sheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?55 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe#, acc, and reset# (note 2) . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 9. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 10. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 9. maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c supply voltages v cc (regulated voltage range) . . . . . . . . . . . 3.0?3.6 v v cc (full voltage range). . . . . . . . . . . . . . . . . 2.7?3.6 v v io (note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65?3.0 v notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. see ordering information section for valid v cc /v io range combinations. the i/os cannot go to 3 v when v io = 1.8 v. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 10. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 11. maximum positive overshoot waveform
february 1, 2007 25301c5 am29lv640mu 37 data sheet dc characteristics cmos compatible notes: 1. the i cc current listed is ty pically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. if v io < v cc , maximum v il for ce# and dq i/os is 0.3 v io . if v io < v cc , minimum v ih for ce# and dq i/os is 0.7 v io . maximum v ih for these connections is v io + 0.3 v 6. v cc voltage requirements. 7. v io voltage requirements. v cc = 3 v and v io = 3 v or 1.8 v. when v io is at 1.8 v, i/os cannot operate at 3 v. 8. not 100% tested. 9. includes ry/by#. parameter symbol parameter description test conditions min typ max unit i li input load current (note 1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i cc1 v cc active read current (notes 1, 2) ce# = v il, oe# = v ih 5 mhz 15 20 ma 1 mhz 15 20 i cc2 v cc initial page read current (notes 1, 2) ce# = v il, oe# = v ih 30 50 ma i cc3 v cc intra-page read current (notes 1, 2) ce# = v il, oe# = v ih 10 20 ma i cc4 v cc active write current (notes 2, 3) ce# = v il, oe# = v ih 50 60 ma i cc5 v cc standby current (note 2) ce#, reset# = v cc 0.3 v 1 5 a i cc6 v cc reset current (note 2) reset# = v ss 0.3 v 1 5 a i cc7 automatic sleep mode (notes 2, 4) v ih = v cc 0.3 v; v il = v ss 0.3 v 15a v il1 input low voltage 1(notes 5, 6) ?0.5 0.8 v v ih1 input high voltage 1 (notes 5, 6) 0.7 x v cc v cc + 0.5 v v il2 input low voltage 2 (notes 5, 7) ?0.5 0.3 x v io v v ih2 input high voltage 2 (notes 5, 7) 0.7 x v io v io + 0.5 v v hh voltage for acc program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage (note 9) i ol = 4.0 ma, v cc = v cc min = v io 0.15 x v io v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min = v io 0.85 v io v v oh2 i oh = ?100 a, v cc = v cc min = v io v io ?0.4 v v lko low v cc lock-out voltage (note 8) 2.3 2.5 v
38 am29lv640mu 25301c5 february 1, 2007 data sheet test conditions table 12. test specifications note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms 2.7 k c l 6.2 k 3.3 v device under te s t note: diodes are in3064 or equivalent figure 12. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 13. input waveforms and measurement levels
february 1, 2007 25301c5 am29lv640mu 39 data sheet ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 11 and ta b l e 1 2 for test specifications. parameter description test setup speed options jede cstd. 90r 101, 101r 112 112r 120 120r unit t avav t rc read cycle time (note 1) min 90 100 110 120 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 110 120 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 110 120 ns t pac c page access time max253030403040ns t glqv t oe output enable to output delay max 25 30 30 40 30 40 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 14. read operation timings
40 am29lv640mu 25301c5 february 1, 2007 data sheet ac characteristics note: toggle a0, a1, a2. figure 15. page read timings a21 - a2 ce# oe# a1 - a0 data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
february 1, 2007 25301c5 am29lv640mu 41 data sheet ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 16. reset timings
42 am29lv640mu 25301c5 february 1, 2007 data sheet ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words programmed. 4. effective write buffer specification is based upon a 16-word write buffer operation. 5. word programming specification is based upon a single word programming operation not utilizing the write buffer. 6. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc. 7. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options jedec std. description 90r 101 112 120 unit t avav t wc write cycle time (note 1 ) min 90 100 110 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2 , 3 ) typ 352 s effective word program time, using the write buffer (notes 2 , 4 ) ty p 2 2 s effective accelerated word program time, using the write buffer (notes 2 , 4 ) typ 17.6 s single word program operation (note 2 , 5 ) typ 100 s accelerated single word programming operation (note 2 , 5 ) ty p 9 0 s t whwh2 t whwh2 sector erase operation (note 2 ) typ 0.5 sec t vhh v hh rise and fall time (note 1 )min250ns t vcs v cc setup time (note 1 ) min 50 s t rb write recovery time from ry/by# min 0 ns t busy we# high to ry/by# low max 90 100 110 120 ns t poll program valid before status polling (note 7 )max 4 s
february 1, 2007 25301c5 am29lv640mu 43 data sheet ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa t poll note: pa = program address, pd = program data, d out is the true data at the program address. figure 17. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 18. accelerated program timing diagram
44 am29lv640mu 25301c5 february 1, 2007 data sheet ac characteristics note: sa= sector address (for sector erase), va= valid addre ss for reading status data (s ee ?write operation status?). figure 19. chip/sector erase operation timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy
february 1, 2007 25301c5 am29lv640mu 45 data sheet ac characteristics we# ce# oe# high z t oe high z dq15 and dq7 dq14?dq8, dq6?dq0 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc t poll note: va = valid address. illustration shows first status cycle af ter command sequence, last stat us read cycle, and array data read cycle. figure 20. data# polling timings (during embedded algorithms)
46 am29lv640mu 25301c5 february 1, 2007 data sheet ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not requir ed for dq6. illust ration shows first two status cycle af ter command sequence, last status read cycle, and array data read cycle figure 21. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase- suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 22. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
february 1, 2007 25301c5 am29lv640mu 47 data sheet ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time fo r temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector group unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 23. temporary sector group unprotect timing diagram
48 am29lv640mu 25301c5 february 1, 2007 data sheet ac characteristics sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih * for sector group protect, a6:a0 = 0xx0010. for sector group unprotect, a6:a0 = 1xx0010. figure 24. sector group protect and unprotect timing diagram
february 1, 2007 25301c5 am29lv640mu 49 data sheet ac characteristics alternate ce# cont rolled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for mo re information. write buffer program is typical per word. 3. for 1?16 words programmed. 4. effective write buffer specification is based upon a 16-word write buffer operation. 5. word programming specification is based upon a single word programming operation not utilizing the write buffer. 6. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc. 7. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options jedec std. description 90r 101, 101r 112, 112r 120, 120r unit t avav t wc write cycle time (note 1 ) min 90 100 110 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2 , 3 ) ty p 3 5 2 s effective word program time, using the write buffer (notes 2 , 4 ) ty p 2 2 s effective accelerated word program time, using the write buffer (notes 2 , 4 ) ty p 1 7 . 6 s single word program (note 2 , 5 )typ 100 s accelerated single word programming operation (note 2 , 5 ) ty p 9 0 s t whwh2 t whwh2 sector erase operation (note 2 ) typ 0.5 sec t rh reset # high time before write (note 1 ) min 50 ns t poll program valid before status polling (note 7 ) max 4 s
50 am29lv640mu 25301c5 february 1, 2007 data sheet ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7#, d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy dq15 t poll notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 25. alternate ce# controlled write (erase/program) operation timings
february 1, 2007 25301c5 am29lv640mu 51 data sheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc . programming specifications assume that all bits are programmed to 00h. 2. maximum values are measured at v cc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. word programming specification is based upon a single word programming operation not utilizing the write buffer. 4. for 1-16 words programmed in a single write buffer programming operation. 5. effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation. 6. in the pre-programming step of the embedded erase al gorithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to execute the command sequence(s) for the program command. see table 10 for further information on command definitions. 8. the device has a minimum erase and pr ogram cycle endurance of 100,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 15 sec excludes 00h programming prior to erasure (note 6) chip erase time 64 128 sec single word program time (note 3) 100 800 s excludes system level overhead (note 7) accelerated single word program time (note 3) 90 720 s total write buffer program time (note 4) 352 1800 s effective word program time, using the write buffer (note 5) 22 113 s total accelerated write buffer program time (note 4) 282 1560 s effective accelerated word program time, using the write buffer (note 4) 17.6 98 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma
52 am29lv640mu 25301c5 february 1, 2007 data sheet tsop pin and fine-pitch bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter symbol parameter desc ription test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf fine-pitch bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf fine-pitch bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf fine-pitch bga 3.9 4.7 pf parameter description t est conditions min unit minimum pattern data retention time 150 c10years 125 c20years
february 1, 2007 25301c5 am29lv640mu 53 data sheet physical dimensions laa064?64-ball fortified ball grid array ( f bga) 13 x 11 mm package
54 am29lv640mu 25301c5 february 1, 2007 data sheet physical dimensions fbe063?63-ball fine-pitch ball gr id array (fbga) 12 x 11 mm package dwg rev af; 10/99
february 1, 2007 25301c5 am29lv640mu 55 data sheet revision summary revision a (aug ust 3, 2001) initial release as abbreviated advance information data sheet. revision a+1 (september 12, 2001) global changed description of chip-scale package from 63-ball fbga to 64-ball fortified bga. ordering information changed package part number designation from wh to pc. physical dimensions added the ts056 and laa064 packages. revision a+2 (o ctober 3, 2001) global added information for wp# protected devices (lv640mh/l). clarified v cc and v io ranges. connection diagrams changed rfu (reserved for future use) to nc (no con- nection). added 63-ball fbga drawing. ordering information added h and l valid combinations for wp# protected devices. changed voltage operating range for 90 ns device. revision b (march 19, 2002) global expanded data sheet to full specification version. starting with this revision , the data sheet will only con- tain specifications for the am29lv640mu part number. for am29lv640mh/l part number specifications, refer to publication number 26191. revision b+1 (april 26, 2002) global deleted references to word mode. mirrorbit 64 mbit device family deleted am29lv641mt/b. figure 2, in-system sector group protect/unprotect algorithms modified to show a2, a3 address requirements. sector protection/unprotection deleted references to alternate method of sector pro- tection. autoselect command substituted text with id code table for easier refer- ence. table 10, command definitions combined notes 4 and 5 from revision b. corrected number of cycles indicated for write-to-buffer and au- toselect device id command sequences. revision b+2 (august 5, 2002) mirrorbit 64 mbit device family added 64 fortified bga to lv640mu device. alternate ce# controlled erase and program operations added t rh parameter to table. erase and program operations added t busy parameter to table. figure 16. program operation timings added ry/by# to waveform. tsop and bga pin capacitance added the fbga package. program suspend/program resume command sequence changed 15 s typical to maximum and added 5 s typical. erase suspend/erase resume commands changed typical from 20 s to 5 s and added a maxi- mum of 20 s. revision b+3 (september 10, 2002) product selector guide added note 2. ordering information added note 1. connection diagram deleted a-1 from pin g7. sector erase command sequence deleted statement that describes the outcome of when the embedded erase operation is in progress.
56 am29lv640mu 25301c5 february 1, 2007 data sheet revision b+4 ( february 16, 2003) distinctive characteristics corrected performance characteristics. product selector guide added note 2. ordering information corrected valid combination to reflect speed option changes. added note. ac characteristics removed 90r speed option. added note input values in the t whwh 1 and t whwh 2 parameters in the erase and program options table that were previ- ously tbd. also added notes 5 and 6. input values in the t whwh 1 and t whwh 2 parameters in the alternate ce# controlled erase and program op- tions table that were previously tbd. also added notes 5 and 6. erase and programming performance input values into table that were previously tbd. added note 4. revision c (march 11, 2003) product selector guide and ac characteristics, read only operations table added separate values for the 112 and 120 ns speed options in the page access times and oe# access time. ordering information removed note from sector architecture. table 3. autoselect codes, (high voltage method) updated dq15 to dq0 for sector protection verifica- tion and secured silicon sector indicator bit. secured siliconsector flash memory region updated second bu llet in customer lockable section. added figure 3. command definitions updated first paragraph. table 3. autoselect codes, (high voltage method) table 10. command definitions corrected note #10 to read 98h for factory locked and 18h for not factory locked. operating ranges added a v cc for regulated voltage and added standard voltage range title for remaining v cc. cmos compatible added i lr parameter symbol. updated i cc parameter symbol. revision c+1 (june 12, 2003) ordering information added 90r speed grade, modified note. erase and programming performance modified table, inserted values for typical. revision c+2 (febr uary 13, 2004) writing commands/command sequence removed byte reference. word/byte program command sequence removed byte reference. erase suspend/erase resume commands added note on flash device performance during suspend/erase mode . table 10: command definitions replaced the addr information for program/erase suspend and program/erase resume from ba to xxx. ac characteristics - erase and program operations, and alternate ce# controlled erase and program operations added t poll information. ac characteristics figures - program operation timings, data# polling timings (during embedded algorithms, and alternate ce# controlled write (erase/program) operation timings updated figures with t poll information. erase and programming performance removed byte reference. incorporated comments 6 & 7 to table. trademarks updated. revision c + 3 (august 23, 2004) added max programming specifications. added notation referencing superseding documenta- tion.
february 1, 2007 25301c5 am29lv640mu 57 data sheet revision c + 4 (december 13, 2005) global this product has been retired and is not available for designs. for new and current designs, s29gl064a supersedes am29lv640m u and is the factory-recom- mended migration path. please refer to the s29gl064a datasheet for specifications and ordering information. availability of th is document is retained for reference and historical purposes only. revision c5 (february 1, 2007) global changed secsi sector to secured silicon sector. ac characteristics erase and program operations table: changed t busy to a maximum specification. colophon the products described in this document ar e designed, developed and manufactured as c ontemplated for general use, including wit hout limita- tion, ordinary industrial use, general offi ce use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe phys ical damage or other loss (i.e ., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersi ble repeater and artificial satel lite). please note that spansion inc. will not be liable to you and/or any third party for any clai ms or damages arising in c onnection with above-mentioned us es of the products. any se miconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your faci lity and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in th is document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administrati on regulations or the applicable laws of any other country, the prior au- thorization by the respective government entit y will be required for export of those products. trademarks copyright ? 2001?2005 advanced micro devices, inc. all rights reserv ed. amd, the amd logo, and combinations thereof are registe red trade- marks of advanced micro devices, inc. expressflash is a trademar k of advanced micro devices, in c. product names used in this pu blication are for identification purposes only and may be trademarks of their respective companies. copyright ? 2006?2007 spansion inc. all rights reserved. spansion, the spansion logo, mirrorbit, ornand, hd-sim, and combinatio ns thereof are trademarks of spansion inc. ot her names are for informational purposes only and may be trademarks of their respecti ve owners.

▲Up To Search▲

Price & Availability of AM29LV640MU90RWHI

	To Download AM29LV640MU90RWHI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .